The present invention relates to electrically rewritable non-volatile memories which employ a ferroelectric material.
Recently utilized semiconductor non-volatile memories of the prior art include EPROMs (Erasable Programmable Read-Only Memories or ultraviolet ray erasable non-volatile memories) and EEPROMs (Electrically Erasable Programmable Read-Only Memories or electrically rewritable non-volatile memories) which are typically based on MIS transistors and take advantage of the phenomenon that a surface potential of a silicon substrate is modulated by injecting electric charges from the silicon substrate into traps within an insulating gate or into a floating gate.
These non-volatile memories have certain inherent shortcomings in that, for example, the voltage required for rewriting is typically as high as 20 V or thereabouts, and the rewrite time is relatively long (e.g., several tens of milliseconds in the case of the EEPROM). In addition, the number of information rewriting operations is as small as approximately 10.sup.5 times. Therefore, repetitive use of such a memory presents a good number of problems.
Non-volatile memories which employ ferroelectric substances capable of having their polarization electrically inverted have a possibility of being ideal, because their write time is in principle the same as their read time, and because the polarization is maintained even when turning off the power supply.
Geometries of non-volatile memories using ferroelectric substances have already been described in, e.g., U.S. Pat. No. 4,149,302 where a capacitor composed of a ferroelectric substance is integrated on a silicon substrate, and U.S. Pat. No. 3,832,700 where a film of a ferroelectric substance is disposed at a gate of an MIS transistor. Still another geometry for the non-volatile memory which has recently been proposed is described in a paper by Kinney, et al., published in IEDM 87 at pages 850-851. According to this proposal, films are laminated on an MOS semiconductor device as depicted in FIG. 11 of the accompanying drawing.
FIG. 11 is a cross-sectional view illustrating the structure of a ferroelectric capacitor memory cell formed on a p-type silicon substrate 1101 and isolated from adjacent components by an LOCOS field oxide film 1101.
The cell itself is composed of an MOS transistor which is formed by an N-type diffused layer 1103 serving as a source, an N-type diffused layer 1104 serving as a drain, a gate electrode 1105, and an inter-layer insulating film 1106. The cell further includes a film 1108 of ferroelectric material sandwiched between two electrodes 1107 and 1109 to create a ferroelectric capacitor on insulating film 1106 above gate 1105. The cell is completed by a second inter-layer insulating film 1110 and an aluminum connection electrode 1111.
A structure of the type shown in FIG. 11 offers the advantage that it can be placed in a small area. However, manufacture requires a large number of steps to additionally form the upper and lower electrodes, a ferroelectric material film and a second inter-layer insulating film as compared with an ordinary semiconductor device. Supposing that a ferroelectric material film exhibiting satisfactory properties can be obtained, there still exists the problem of cost resulting primarily from the number of manufacturing steps.